Generally, semiconductor devices include a plurality of circuits that form an integrated circuit including chips, thin film packages and printed circuit boards. Integrated circuits (ICs) can be useful for computers and electronic equipment and can contain millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate. For the device to be functional, a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the device. Efficient routing of these signals across the device can become more difficult as the complexity and number of integrated circuits are increased. Thus, the formation of multilevel or multilayered interconnect schemes such as, for example, dual damascene wiring structures, have become more desirable due to their efficacy in providing high speed signal routing patterns between large numbers of transistors on a complex semiconductor chip. Within the interconnect structure, metal vias run perpendicular to the silicon substrate and metal lines run parallel to the silicon substrate.
Presently, interconnect structures formed on an integrated circuit chip consists of at least about 2 to 8 or more wiring levels fabricated at a minimum lithographic feature size designated about 1× (referred to as “thinwires”) and above these levels are about 2 to 4 or more wiring levels fabricated at a thickness and pitch equal to about 2× and/or about 4× the minimum thickness and pitch of the thinwires (referred to as “fatwires”). In one class of structures, the thinwires are formed in a low dielectric constant (k) organosilicate glass (OSG) dielectric layer that includes atoms of Si, C, H and O, and the fatwires are made in a silicon dioxide dielectric layer having a dielectric constant of about 4. In anther class of structures, thinwires are formed in one type of low dielectric constant (k) organosilicate glass (OSG, SiCOH), some fatwires are made in the same or a different variant of SiCOH, and some fatwires may be made of silicon dioxide or silicon dioxide doped with fluorine. Additionally, other values of multipliers such as 1.4×, 6×, 8×, etc. have been used for wiring levels rather than just the traditional 2× and 4× fatwires.
With microelectronics industry's gradual transition to porous dielectrics (k of less than 2.5) for interconnect integration, new integration challenges have emerged. One key issue is related to the poor mechanical properties of the low k dielectrics. The very low modulus, E, typically less than 5 GPa, contributes to the undesirable deformation of the previously constructed profile shapes in the ILD material during the physically aggressive liner sputtering process that is commonly practiced in semiconductor processing. A typical defect induced by aggressive liner sputtering is the unacceptable roughening of the trench bottoms. This raises concerns about the integrity of the liner coverage at these roughened interfaces, related plating defectivity and, most importantly, the stress migration/electromigration reliability.
U.S. Pat. No. 5,619,071 to Myers et al. disclose a high performance and reliable interconnect structure for preventing via delamination. Specifically, Myers et al. provide a multilayer interconnect structure comprising a titanium aluminide electromigration shunt layer, an aluminum alloy bulk conductor and a titanium aluminide capping layer formed on an insulating layer of a semiconductor substrate. A second insulating layer is formed on and around the multilayer interconnection. A via connection comprising tungsten has a first portion with a first width which extends through the insulating layer and through the capping layer of the interconnection line, and a second portion wider than the first portion, which is formed on the bulk conductor and underneath the capping layer to thereby lock the via connection into the interconnection.
U.S. Pat. No. 6,548,905 to Park et al. (corresponding to U.S. Publication No. 2002/0109234 A1) provides a semiconductor device in which electromigration is prevented, reliability concerns are reduced and resistance of the via contact interface at a multilayer Cu line is lowered. In accordance with Park et al., the semiconductor device having these properties comprises a lower copper line formed on a substrate; an interlayer insulating layer formed on the lower copper line; an upper copper line formed on the interlayer insulating layer; a copper via contact formed within the interlayer insulating layer for electrically connecting the lower copper line and the upper copper line; a concave recess formed within the lower copper line, the concave recess being vertically aligned and arranged below the copper via contact; and a patterned barrier layer formed at a bottom portion of the concave recess, wherein the lower copper line and the copper via contact are directly electrically connected at an interface along sides of the concave recess.
It is noted that in Park et al. it is desired that the etch into the Cu line be half the depth of the line and 1.25× the width of the definition via. This significant depth leads to significant undercut and can also lead to excessive over-etch (based on statistical process variations in high-volume manufacturing) that could cause undesired voiding of the subsequent Cu metal fill. Furthermore, Park et al. design their structure such that liner coverage is substantially absent on the sidewalls of the recess into the Cu line in order that the Cu via to Cu line contact will occur with their stated objective of the elimination of the additional electrical resistivity that a liner barrier material introduces into the via/line contact. Moreover, the etchant behavior suggested in Park et al. will produce a structure with a significant undercut behavior that would be detrimental to a reliable contact design.
FIGS. 1A-1E are pictorial representations depicting the prior art process disclosed in Park et al. FIG. 1A shows a structure 10 formed just prior to the construction of the copper recess. Specifically, prior art structure 10 includes a lower interlevel dielectric (ILD) 12 which includes a Cu wiring region 14 embedded therein. For clarity, the liner coverage of the Cu wiring region 14 is not illustrated, but it is normally present. The structure 10 also includes a first dielectric cap 16 that is located over the lower ILD 12 and the Cu wiring region 14; the first dielectric cap 16 is opened at this point of the prior art process exposing a surface of the Cu wiring region 14. Atop the first dielectric cap 16 is an upper ILD 18 that has a line opening 20 and a via opening 22 located therein. The materials and processing steps used in forming the prior art structure 10 are conventional and are well known in the art.
Prior art FIG. 1B illustrates the structure 10 after the Cu wiring region 14 has been recessed by a conventional etching process. Reference numeral 24 denotes the recessed opening provided in the Cu wiring region 14. In FIG. 1B, letter “a” refers to a critical diameter of the via opening 22, letter “b” refers to the undercut beneath the dielectric cap 16 during the Cu etch, letter “c” refers to the depth of the etch into the Cu wiring region 14, and letter “d” denotes the full thickness of the Cu wiring region 14. In Park et al., it is disclosed that 1.25a=c, c=b, and c=d/2. That is, Park et al. disclose that the recess etched into the metal line should be half the depth of the line and 1.25× the width of the via.
Prior art FIG. 1C illustrates the structure of FIG. 1B after liner and seed liners have been deposited. It is noted that the liner 26 is discontinuous because of the difficulty in bridging the large undercut that is provided by the Park et al. process; the sides of the undercut denoted by reference numeral 28 are not covered by liner 26 (see FIG. 1C). Note that in FIG. 1C the liner (26) deposition is line of sight and does not extend beyond the direct aperture of the via opening. In Park et al., the very large etch recess results in this discontinuous liner 26 and enables increased surface area for Cu-to-Cu connection. An unfortunate result of this very large etch recess is that the electrical connection necessary for efficient electrolytically plated copper fill of this very large etch recess is very difficult to achieve. The typical liner and seed for the subsequent metallization structure become discontinuous at the upper part of the etched recess and thus the electrical connection for the electrochemical fill of this recess must find alternative pathways for electrical circuit closure. Park et al. argue that a sputtering process will not provide sufficient electrical connection for proper electroplating of their concave recess and suggest the use of a CVD copper seed layer to provide electrical connection to the discontinuous copper line in order to enable the electrochemical plating of their concave recess. However, it has been found that a CVD Cu seed layer has poor adhesion to many materials, both dielectric and conductive and this consequently leads to poor electromigration reliability of the Cu interconnect.
Prior art FIG. 1D shows the ideal structure after Cu 30 deposition which fills the recessed opening 24, the via opening 22, and the line opening 20. Prior art FIG. 1E illustrates the structure after planarization and deposition of a second dielectric cap 32. As shown, the second dielectric cap 32 covers the Cu filled line and the upper ILD 18.
In view of the above, there is a need for providing a structure and methods of chemically formed anchored metallic vias in which the depth of the anchoring is substantially less than ½ the anchored—to interconnect thickness—that in turn requires a Cu etch that is highly controllable on the nanometer scale. There is also a need for providing an etched recess with an improved electrical pathway through the use of a sufficiently continuous liner or non-CVD Cu seed layer for subsequent electrochemical deposition of the metal fill; whereby, the sufficiently continuous liner or seed layer enables the fill of the recess etched into the lower copper line resulting in a device that meets a high level of functional reliability. The applicants of the present application have determined that the electrical pathway may be maintained by a sufficiently continuous liner if the etch recess is designed to a different dimensional ratio such that the resultant IR drop (where I=current, R=resistance) from the deposited liner or seed layer is sufficiently small to maintain a proper current level for copper fill, and that this can produce a reliable device structure.